This invention relates to computer systems and microprocessors, and more particularly to a multimedia execution unit incorporated within a microprocessor for accommodating high-speed multimedia applications. The invention further relates to extreme value functions and vector processing implemented within microprocessor based systems.
Microprocessors typically achieve increased performance by partitioning processing tasks into multiple pipeline stages. In this manner, microprocessors may independently be executing various portions of multiple instructions during a single clock cycle. As used herein, the term xe2x80x9cclock cyclexe2x80x9d refers to an interval of time during which the pipeline stages of a microprocessor perform their intended functions. At the end of the clock cycle, the resulting values are moved to the next pipeline stage.
Microprocessor based computer systems have historically been used primarily for business applications, including word processing and spreadsheets, among others. Increasingly, however, computer systems have evolved toward the use of more real-time applications, including multimedia applications such as video and audio processing, video capture and playback, telephony and speech recognition. Since these multimedia applications are computational intensive, various enhancements have been implemented within microprocessors to improve multimedia performance. For example, some general purpose microprocessors have been enhanced with multimedia execution units configured to execute certain special instructions particularly tailored for multimedia computations. These instructions are often implemented as xe2x80x9cvectoredxe2x80x9d instructions wherein operands for the instructions are partitioned into separate sections or vectors which are independently operated upon in accordance with the instruction definition. For example, a vectored add instruction may include a pair of 32-bit operands, each of which is partitioned into four 8-bit sections. Upon execution of such a vectored add instruction, corresponding 8-bit sections of each operand are independently and concurrently added to obtain four separate and independent addition results. Implementation of such vectored instructions in a computer system furthers the use of parallelism, and typically leads to increased performance for certain applications.
One type of commonly employed function in multimedia applications is a compare function. A compare function is typically implemented though the execution of a compare instruction which compares the value of one operand against another to determine whether the value of the first is greater than, equal to, or less than the other. A compare instruction may be treated as a vectored instruction wherein corresponding sections of associated operands are compared independently of other sections of the operands.
Another set of functions commonly utilized in multimedia processing are the extreme value functions. As used herein, xe2x80x9cextreme value functionsxe2x80x9d are those functions which return either a minimum value selected among a plurality of values, or a maximum value selected among a plurality of values as a result of the function. In typical multimedia systems, a minimum value or a maximum value is obtained through the execution of several sequentially executed instructions. For example, a compare instruction may first be executed to determine the relative magnitudes of a pair of operand values, and subsequently a conditional branch instruction may be executed to determine whether a move operation must be performed to move the extreme value to a destination register or other storage location. These sequences of commands are common in multimedia applications, such as clipping algorithms in graphics rendering systems. Since extreme value functions are implemented through the execution of multiple instructions, however, a relatively large amount of processing time may be consumed by such operations.
It would therefore be desirable to provide a multimedia execution unit in a microprocessor which is capable of obtaining an extreme value through the execution of a single instruction. It would further be desirable to provide a multimedia execution unit with an efficient hardware implementation of the extreme value instructions.
The problems outlined above are in large part solved by an execution unit in accordance with the present invention. In one embodiment, an execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operands. If the decoded opcode value received by the comparator indicates that the first instruction is either a compare or extreme value function, the comparator conveys one or more control signals to the multiplexer for the purpose of selecting an ouput of the multiplexer as the result of the first instruction. If the first instruction is one of a plurality of extreme value instructions, the one or more control signals conveyed by the comparator unit select between the first operand and second operand to determine the result of the first instruction. If the first instruction is one of a plurality of compare instructions, the one or more control signals conveyed by the comparator unit select between the first and second constant value to determine the result of the first instruction. In the case of the compare instructions, the value of the first and second constants may be advantageously chosen in order to form a mask for use by subsequent instructions. In another embodiment, a similar execution unit is provided which handles vector operands.
The extreme value functions are thus implemented in a single instruction. This advantageously results in improved performance for these instruction, which are particularly important in multimedia applications. An efficient hardware implementation is also achieved as the circuitry used for the extreme value operations is also shared by a plurality of compare operations.
Broadly speaking, the present invention contemplates a microprocessor configured to execute a first instruction, wherein an encoded representation of said first instruction includes an opcode field, a first operand field, and a second operand field. The microprocessor comprises an execution unit coupled to receive a decoded value of the opcode field, a first operand specified by a value of the first operand field, and a second operand specified by a value of the second operand field, wherein the execution unit is configured to perform an extreme value operation on the first operand and the second operand in response to receiving the decoded value of the opcode field. The execution unit is further configured to convey an output value of the extreme value operation as a result of the first instruction.
The present invention further contemplates an execution unit in a microprocessor for executing a first instruction, wherein an encoded representation of the first instruction includes an opcode field, a first operand field, and a second operand field. The execution unit comprises a first input register coupled to receive a first operand specified by a value of the first operand field and a second input register coupled to receive a second operand specified by a value of the second operand field. The execution further comprises a comparator unit coupled to receive the first operand from the first input register and the second operand from the second input register. The comparator unit is coupled to receive a decoded opcode value of the opcode field on a decoded opcode bus. Still further, the execution unit comprises a multiplexer coupled to receive a plurality of inputs including the first operand from the first input register, the second operand from the second input register, a first constant value, and a second constant value. The multiplexer is configured to select one of the plurality, of inputs to be conveyed as a result of the first instruction in response to receiving one or more control signals from the comparator unit. The comparator unit is configured to generate the one or more control signals in response to receiving the decoded opcode value, and, if the decoded opcode value indicates that the first instruction is one of a plurality of extreme value instructions, the one or more control signals are usable to select either the first operand or the second operand as the output value. If the decoded opcode value indicates that the first instruction is one of a plurality of compare instructions, the one or more control signals are usable to select either the first constant value or the second constant value as the output value.
The present invention still further contemplates an execution unit in a microprocessor for executing a first instruction, wherein an encoded representation of the first instruction includes an opcode field, a first operand field, and a second operand field. The execution unit comprises a first input register coupled to receive a first operand specified by a value of the first operand field, wherein the first operand includes a first vector value followed by a second vector value, as well as a second input register coupled to receive a second operand specified by a value of the second operand field, wherein the second operand includes a third vector value followed by a fourth vector value. The execution unit further comprises a comparator unit coupled to receive the first operand from the first input register and the second operand from the second input register. The comparator unit is coupled to receive a decoded opcode value of the opcode field on a decoded opcode bus. Additionally, the execution unit comprises a first multiplexer coupled to receive a first plurality of inputs including the first vector value from the first input register, the third vector value from the second input register, a first constant value, and a second constant value. The first multiplexer is configured to select one of the first plurality of inputs to be conveyed as a first portion of a vector result of the first instruction in response to receiving a first set of control signal values from the comparator unit. The comparator unit is further configured to generate the first set of control signal values in response to receiving the decoded opcode value. If the decoded opcode value indicates that the first instruction is one of a plurality of extreme value instructions, the first set of control signal values are usable to select either the first vector value or the third vector value as the first portion of the vector result. If the decoded opcode value indicates that the first instruction is one of a plurality of compare instructions, the first set of control signal values are usable to select either the first constant value or the second constant value as the first portion of the vector result.
The present invention additionally contemplates a method for executing a first instruction within an execution unit of a microprocessor, wherein an encoded representation of the first instruction includes an opcode field, a first operand field, and a second operand field. The method comprises conveying a first plurality of inputs to a comparator unit within the execution unit, wherein the first plurality of inputs includes a first operand specified by a value of the first operand field, a second operand specified by a value of the second operand field, and a decoded opcode value which corresponds to an encoded opcode value of the opcode field. The method further comprises conveying a second plurality of inputs to a multiplexer within the execution unit, wherein the second plurality of inputs includes the first operand, the second operand, a first constant value, and a second constant value. Still further, the method comprises generating a set of control signal values from the comparator unit in response to receiving the first plurality of inputs. The method next comprises conveying one of the second plurality of inputs from the multiplexer as a result of the first instruction in response to receiving the set of control signal values. The result is selected from the first operand and the second operand according to the set of control signal values if the decoded opcode value indicates that the first instruction corresponds to one of a plurality of extreme value instructions. The result is selected from the first constant value and the second constant value according to the set of control signal values if the decoded opcode value indicates that the first instruction corresponds to one of a plurality of compare instructions.
Finally, the present invention contemplates a microprocessor configured to execute a first instruction. The microprocessor comprises an instruction cache configured to store an encoded representation of the first instruction, wherein the encoded representation includes an opcode field, a first operand field, and a second operand field. The microprocessor further comprises a decode unit coupled to receive the encoded representation of the first instruction from the instruction cache, wherein the decode unit is configured to generate a decoded opcode value in response to receiving a value of the op code field. The microprocessor still further comprises an execution unit coupled to the decode unit, wherein the decode unit is further configured to cause a first operand and a second operand to be conveyed to the execution unit. The first operand is specified by a value of the first operand field, while the second operand is specified by a value of the second operand field.
The execution unit includes a first input register coupled to receive a first operand specified by a value of the first operand field, as well as a second input register coupled to receive a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit coupled to receive the first operand from the first input register and the second operand from the second input register, The comparator unit is further coupled to receive a decoded opcode value of the opcode field on a decoded opcode bus. The execution unit still further includes a multiplexer coupled to receive a plurality of inputs including the first operand from the first input register, the second operand from the second input register, a first constant value, and a second constant value. The multiplexer is configured to select one of the plurality of inputs to be conveyed as a result of the first instruction in response to receiving a control signal value from the comparator unit. The comparator unit is configured to generate the control signal value in response to receiving the decoded opcode value. If the decoded opcode value indicates that the first instruction is one of a plurality of extreme value instructions, the control signal value is usable to select either the first operand or the second operand as the output value. If the decoded opcode value indicates that the first instruction is one of a plurality of compare instructions, the control signal is usable to select either the first constant value or the second constant value as the output value.